1. Field of the Invention
The present invention relates in general to Redundant Array of Independent Disks (RAID) systems, and in particular to a subsystem such as a RAID controller.
2. Statement of the Problem
RAID (Redundant Array of Independent Disks) storage systems are well known in the art. They provide a high-speed, fault-tolerant hard disk memory. RAID systems protect against the failure of an individual disk drive by distributing the data redundantly over multiple disks. If one disk fails, the data can be recovered from the other disks.
The closest prior art RAID system 100 will be described herein in reference to FIG. 1. RAID system 100 includes a plurality of hard disks 130. A RAID controller 110 is used to control the input and output of a data stream on I/O line 140 to the disks 130. The controller determines to which disks a given packet in the data stream will be written, and retrieves requested data from the correct disk(s). Generally, a controller microprocessor 115 performs this function. To increase the fault tolerance of the storage subsystem, two RAID controllers 110, 120 are used and configured in a redundant manner. Thus, if one controller fails, the other controller can continue to store data in a non-redundant manner at essentially the same speed, or in a redundant manner at slower speed. In the preferred prior art systems, each controller 110, 120 is connected to each of disks 130. In the exemplary RAID system 100 shown, there are twelve disks 130 and each controller 110, 120 has two input/output chips, 111, 112 and 121, 122, respectively. I/O chip 111 in controller 110 is connected to disks 1 through 6 via cabling 150, and I/O chip 112 is connected to disks 7 through 12 via cabling 151; I/O chip 121 in controller 120 is connected to disks 1 through 6 via cabling 154, and I/O chip 122 is connected to disks 7 through 12 via cabling 155. Each cabling system, such as 151, includes appropriate connectors, such as 156 and 157.
In prior art systems 100, the disk I/O system could be any of a large number of prior art communication systems, such as SCCI, SATA, SSA, ATA, FCAL, SAS, etc. I/O chips 111, 112, 121, 122 and cabling systems 150, 151, 154, 155 are determined as known in the art for the protocols for the selected system. In the system 100 shown, a SAS I/Q system has been selected because this results in a system that is closest to the system according to the invention, and therefore makes it easier to understand the invention. In a SAS system, each SAS disk I/O chip, such as 112, includes a plurality of ports, such as 164, each port comprising a transceiver, such as 166. As known in the art, each SAS port 164 is connected via a seven conductor unshielded cable connector, such as 168. As known in the art, four of the wires are two pairs of differential signals, one pair carrying signals in each direction, and three of the wires are ground signals. Prior art controller chips 110, 120 preferably each include a controller chip set 114, 124, respectively; a host I/O chip 117, 127, respectively; and a battery 118, 126, respectively. Each controller, such as 110, also includes appropriate internal electrical connections, such as 148, 149, and 143 as known in the art.
To increase the speed of access to the disk drives, in each controller 110, 120 both read and write data are cached to a controller memory 113, 125, respectively. To increase the overall throughput of the memory subsystem, the two controllers 110, 120 are set up in an active-active configuration in which both controllers simultaneously service storage requests. For two RAID controllers to function completely redundantly in an active-active configuration, the write cache must be synchronized between the two controllers. Thus, if a controller fails during a cached write operation, the other controller has enough information to complete the write operation. To maintain cache synchronization, a link 160 between the two controllers is required. Very high speed is required of this link, since the link must keep up with the flow of data through the system; in essence, this link defines how fast the system can handle data. In the prior art, very high speed is essentially equivalent to high cost. Thus, the cost of this link makes a significant impact on the overall cost of the controller.
In the prior art, the high-speed link between the controllers has been accomplished with either Gigabit Ethernet or Fibre Channel. Both types of links require a specialized chip 116, 128 in each controller to provide the intracontroller communication, plus appropriate wiring and connectors 143, 144, 170 between the links and the controller system; hence, the high cost of the link. Gigabit Ethernet requires four high-speed differential pairs to be routed through the subsystem backplane and provides approximately 90 Mbytes/sec throughput. Fibre Channel only requires two high-speed differential pairs, and can support approximately 200 Mbytes/sec, though it is considerably more expensive than Gigabit Ethernet. It would be a significant advance in the art if a controller could be provided that was as fast or faster than the prior art links and did not add significantly to the cost of the controller.